1. Field of the Invention
The present invention concerns routing of electrical connections during the design of flip-chip integrated circuits (ICs), and particularly relates to routing of electrical connections from bump pads to input/output devices on an IC.
2. Description of the Related Art
Certain IC chips (or dies), called wire-bond ICs, are fabricated with metal bonding pads along their periphery. These peripheral pads serve as terminals for connecting the die to external signals, including control signals, power and ground. Typically, the wire-bond IC die is mounted within a plastic or ceramic package having multiple pins, and wire connections are made between the die""s bonding pads and the package""s pins. Finally, the package containing the IC die is mounted onto a printed circuit board in a manner so as to establish electrical connections between the pins of the IC and other components on the printed circuit board. In this manner, external signals can be provided to and from the IC die.
However, the foregoing fabrication method has its limitations. First, because only the periphery of the chip is used for external connection pads, the number of such pads for a given sized chip is limited. In particular, advances in technology which permit more and more gates to be placed within a given chip area have resulted in an increased demand for such pads, particularly power and ground pads. In certain cases, the design requires more pads than can be provided solely at the chip""s periphery. Second, when all the pads are provided only at the chip""s periphery, additional routing is required to bring the corresponding signals, particularly power and ground signals, to the interior logic of the chip. Third, in wire-bond chips the wire connections between the die and the package pins introduce additional resistance and inductance which sometimes can impair the chip""s performance.
To overcome these problems, flip-chip techniques recently have been used. One example of a flip-chip configuration is shown in FIG. 1, which provides a cross-sectional view of a flip-chip 100. Referring to FIG. 1, flip-chip 100 includes a semiconductor layer 102, on which are formed transistors, resistors and other electronic devices, as well as some of the electrical connections between such electronic devices. Flip-chip 100 also includes one or more metal layers, such as metal layers 104A and 104B, which are used for providing the bulk of the electrical connections between the electronic devices formed on semiconductor substrate 102. These metal layers generally are used primarily for the longer electrical connections, such as the connections between distant cells. By providing such metal layers, valuable space on the semiconductor layer 102 can be conserved for forming the electronic devices. Flip-chip 100 also includes a top layer 106, on which are formed multiple solder bump terminals, such as solder bump terminal 108, called bump pads. These bump pads are used as the input/output terminals for die 100. As used herein, input/output and I/O refer to input-only, output-only or combined input and input.
Referring to FIG. 1, bump pad 108 contacts redistribution metal layer 107. Redistribution metal layer 107, in turn, connects to metal layer 104B and metal layer 104B connects to metal layer 104A using vias 110. Finally, semiconductor layer 102 connects to metal layer 104A using contacts such as contact 111, thereby completing the electrical connections between bump pads 108 and semiconductor layer 102. Between layers 104B and 107 and between metal layer 104A and the semiconductor substrate 102 are electrically insulating layers 105.
For mounting purposes, flip-chip die 100 typically is xe2x80x9cflippedxe2x80x9d so that top layer 106 faces downward. Top layer 106 then is bonded to a substrate. The substrate may be a passive carrier such as a printed circuit board, or it may be another semiconductor chip. Specifically, each bump pad 108 typically is solder bonded to a corresponding pad on the substrate, thereby forming the required electrical connections. The substrate then is usually bonded directly to a printed circuit board, on which additional flip-chips and/or ICs utilizing other types of packaging are mounted.
FIG. 2 provides a representational illustration of semiconductor substrate 102. The logic circuitry of integrated circuit 100 is formed in the interior portion 120 of the semiconductor substrate 102, while the periphery of semiconductor substrate 102 is used for the I/O devices. The logic portion 120 includes a number of functional circuit blocks that can have different sizes and shapes. The larger blocks can include, for example, central processing units such as CPU 121, read-only memories such as ROM 122, clock/timing units such as clock/timing unit 123, random access memories such as RAMs 124, and I/O units such as I/O unit 125 for providing an interface between CPU 121 and various peripheral devices. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries. The logic portion also includes tens of thousands, hundreds of thousands or even millions or additional small cells 126. Each cell 126 represents either a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
Along the periphery of semiconductor substrate 102 are various I/O devices or cells 116. Each such I/O device has connected to it at least one pad 118 which provides a means for electrically connecting to the respective I/O device 116. Pads 118 are, however, different from the bonding pads used in wire-bond IC devices. Rather than being used for wire bonding, pads 118 instead connect to metal traces on redistribution metal layer 107 by using a via. Accordingly, pads 118 generally can be significantly smaller than the wire bonding pads used in wire-bond integrated circuits.
I/O devices 116 receive power and ground by connecting to power (VDD) ring 132 and ground (VSS) ring 133. Similarly, internal logic circuitry 120 receives external power and ground by connecting to power (VDD2) ring 130 and ground (VSS2) ring 131. Typically, VDD2/VSS2 for the internal logic circuitry 120 is provided on a circuit which is separate from the VDD/VSS rings for I/O cells 116 in order to prevent the higher power, and thus noisier, I/O cells from corrupting the logic processing.
To further isolate the power/ground supplies for certain sensitive circuits from the power/ground supplies for noisier circuits, often times cuts are made in the rings (not shown). Each resulting ring segment is then supplied by separate external power/ground signals and can be used to supply a different type of circuit. In addition, although only a single I/O power ring 132 is shown in FIG. 2, mixed-voltage integrated circuits may utilize a different power ring for each different voltage. Moreover, rather than providing power/ground rings 130 to 133 on substrate 102, these power/ground rings often are implemented on a metal layer which is used as a dedicated power plane.
FIG. 3 is a representational view of the bump pad layout and trace connections of flip-chip die 100. As noted above, top layer 106 includes bump pads, such as bump pads 140 to 144. The redistribution layer 107 includes metal traces, such as traces 148, which electrically connect the bump pads to other areas on the die 100. For instance, each of bump pads 140 and 141 is connected using a trace 148 to VDD2 ring 130 and VSS2 ring 131, respectively, which supply the internal logic circuitry 120. Similarly, each of bump pads 142 and 143 is connected using a trace 148 to VDD ring 132 and VSS ring 133, respectively, which supply the I/O cells. Because the power/ground rings in fact are located on a different layer than redistribution metal layer 107 (e.g., metal layer 104A and/or 104B), each such trace in redistribution metal layer 107 does not actually directly connect to a power/ground ring, but instead terminates immediately above the respective power/ground ring. A via is then formed to connect that trace to the power/ground ring. Each of bump pads 144 connects to an I/O device. Bump pads 144 act as the die""s terminals for external I/O signals such as clock, data, address and control signals. Therefore, the trace 148 from each of bump pads 144 terminates just above the corresponding I/O pad.
As shown above, in the flip-chip configuration bump pads can be distributed across the entire surface area of the chip. As a result of placing pads in the interior, as well as near the periphery, connections between the power/ground bump pads and the logic circuitry at the interior of the chip often can be shorter than corresponding connections in wire-bond ICs. Moreover, the flip-chip configuration generally permits the inclusion of more pads without utilizing additional space on the semiconductor layer. Finally, elimination of wire connections between the die and the package substrate often will reduce the inductance and resistance of such connections.
When using flip-chip techniques, a typical IC die often will contain hundreds of bump pads. Routing the signals from each of these bump pads to the appropriate position on the die can therefore become a complicated task. As a result, various methodologies have been developed to reduce this complexity. For instance, one common method utilizes tile-based, or grid-based, placement and routing. According to this method, a bump pad grid is selected based on bump pitch (i.e., required center-to-center bump spacing), and an I/O cell grid is selected based on a standard device width. Once these grids have been established, each bump pad and each I/O cell generally is required to be located within the respective grid slots. By thus constraining placement of bump pads and I/O cells to a finite number of discrete grid slots, the routing problem often can be simplified. For example, in one implementation a routing description between each bump pad slot and I/O slot pair is pre-determined and stored in a library. Accordingly, the description of a trace between any specific bump pad and I/O device can be obtained from the library merely by providing indexes identifying the two grid slots.
FIG. 4 illustrates an example of an electrical connection formed using tile-based routing between a bump pad 144 located in top layer 106 and an I/O device 150 located in semiconductor layer 102. As seen in FIG. 4, I/O device 150 is positioned in I/O slot 161 between I/O slots 160 and 162. Adjacent to I/O device 150 and electrically connected to I/O device 150 is device pad 152, which also is located on semiconductor layer 102. Metal trace 154 is provided on redistribution metal layer 107 and connects bump pad 144 to a point just above device pad 152. A via from redistribution metal layer 107 to semiconductor layer 102 at this point completes the electrical connection from bump pad 144 to device pad 152 for I/O device 150.
While the foregoing tile-based routing method works well for nearly equal-sized I/O devices, when the sizes of the I/O devices vary significantly, problems can arise due to the constraint that I/O devices must lie predefined grid slots. In particular, when a few of the I/O devices are wider than the standard width, it may become necessary to increase the grid slot pitch (i.e., the size of each grid slot) for the entire grid. However, doing so reduces the total number of grid slots, and therefore the number of cells, which can be placed on a given sized die. Often, this will result in a significant amount of wasted peripheral die space, particularly when the vast majority of the I/O devices are of standard width and therefore do not require the larger grid slot.
Similarly, simply maintaining grid slot pitch and using more than one grid slot for these wide I/O devices also can result in inefficient use of die space. For instance, consider the case in which a device pad for the I/O device is required to be located in a grid slot that is only partly occupied by the I/O device. In this event, routing the trace from the bump pad to the partly occupied grid slot generally will preclude use of the remainder of that grid slot for any portion of another I/O device. Moreover, accommodating cases where the device pad occupies portions of two different grid slots may not be possible by merely using conventional tile-based routing.
The present invention addresses these problems by routing an electrical trace to a position corresponding to a pad location for one grid slot and then extending the trace into a position corresponding to a pad location for a second grid slot.
According to one aspect, the invention concerns tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device.
According to a further aspect, the invention performs tile-based routing between a bump pad located on a top layer and an input/output (I/O) device located on a lower layer of a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position directly above a first I/O slot which is at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into a pad area for a second I/O slot and to an area directly above the position obtained for the device pad, the second I/O slot being at least partially occupied by the I/O device. A direct connection is then provided from the trace on the top layer of the IC die to the device pad on the lower layer.
By virtue of the foregoing arrangements, the present invention frequently can accommodate I/O devices that are wider than a single grid slot. At the same time, the invention often can be implemented by making only relatively minor changes to conventional tile-based routing, thereby also maintaining many of the benefits of conventional tile-based routing.
The present invention also addresses the problems of conventional routing by providing an integrated circuit having a trace which includes a first portion routed from a bump pad to a position horizontally offset from the I/O device pad and a second portion which extends the trace to a position corresponding to the device pad.
Thus, according to a further aspect, the invention is a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device. Also provided is an electrically conductive trace, including a first portion between the bump pad and a first position, the first position corresponding to a portion of the I/O device and being horizontally offset from the device pad, and also including a second portion between the first position and a second position corresponding to the device pad.
According to a still further aspect, the invention is a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device having pad space disposed vertically adjacent to a portion of the I/O device, and a device pad disposed within the pad space of the I/O device. Also provided is an electrically conductive trace, including a first portion between the bump pad and a first position corresponding to a portion of the pad space for the I/O device not occupied by said device pad, and also including a second portion between the first position and a second position corresponding to the device pad.
By virtue of the foregoing arrangements, the present invention can often accommodate wide I/O devices with minimal changes to the underlying routing scheme used in the chip design.
The foregoing summary is intended merely to provide a brief description of the general nature of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.